The purpose of the development of 3D IC for semiconductor chips is to dispose more chips on the limited footprint of a printed circuit board. The conventional fabrication processes of 3D IC chip stacking assembly is to acquire Known Good Dice (KGD) firstly, then vertically stack these KGDs to be a 3D IC assembly. However, if there is a failed chip in a 3D IC assembly, the whole 3D IC is discarded since the existing chip codes cannot be changed and the failed chip is included during operation leading to errors.
In a conventional 2D package of semiconductor chips, chips are selected and activated by a controller through Chip Select (CS) which has been designated for individual chips. Therefore, when the control signal CS1 is sent by the controller for the first chip, only the first chip can react, operate, and function. When the control signal CS2 is sent by the controller for the second chip, only the second chip can react, operate, and function.
As the development of 3D IC, chips are vertically stacked on each other and are electrically interconnected by Through Silicon Via (TSV). In order to control the vertically stacked chips with perpendicular electrical interconnection, the conventional control methodology is to implement staggered method to interconnect adjacent chips so that the controller can send commands to a certain chip for certain operations. The signals sent by the controller including commands, addresses, data, etc. are always transmitted from the top chip layer or from the bottom chip layer where the original CS command is designated and sent along with other signals to all chip layers, however, only the selected chip would accept the CS command from the controller and react accordingly. Gillingham taught one of conventional 3D IC chip assemblies referring to US Patent Publication No. US 2011/0050320 A1 for more detail. As described in this patent, the left-side first TSV of the first chip layer is electrically connected to the left-side second TSV of the second chip layer; the left-side second TSV of the first chip layer is electrically connected to the left-side third TSV of the second chip layer. In order to avoid floating of the left-side first TSVs of all chip layers except for the first chip layer which are not connected to any components, the left-side first TSV of each chip layer is not only connected to left-side second TSV of an upper chip layer but also connected to the left-side first TSVs of the upper chip layer. Through the interconnection arrangement, all vertically stacked chip layers with the corresponding array can clearly be defined and signal floating can be avoided.
The about mentioned CS is implemented in 3D IC assembly through staggered interconnection of CS signals achieved by physical 3D IC package structure. An alternative is developed by the coding methodology to replace the corresponding CS signals, i.e., to give each chip layer a corresponding array, an implementation of ID concept, through a sequence generator. Then, the specific ID array is decoded by a decoder to generate an activated signal where the corresponding I/O gates are activated to receive the corresponding signals sent from the controller so that the CS signal sent by the controller is accepted by a certain corresponding chip layer then to accept further commands for further operation.
Basically, the logic of a sequence generator always generates N output values when there are N input values. For example, if there are N input values to input nodes (in0, in1, in2, in3, . . . inN), there are N corresponding output values from output nodes (out0, out1, out2, out3, . . . outN), i.e., the input values and the output values are one-to-one corresponded. Furthermore, each output value is a function sequence of one corresponding input value, for example, output values (out0, out1, out2, out3, . . . outN)=F input values (in0, in1, in2, in3; . . . inN) and not every input value is equal to the corresponding output value, for example, output values (out0, out1, out2, out3, . . . outN)≠input values (in0, in1, in2, in3, . . . inN).
Since the function and the operation of a sequence generator is well-known in the field, therefore, only simple examples are illustrated as follows.
Basically, no matter it is a binary sequence generator or a triplet sequence generator, . . . or even N-bit sequence generator, the desired array is acquired by digital assembly algorithm. An example of input values and output values of a sequence generator is shown in Table 1 as follows.
TABLE 1Chip Layerin1in0out1out000001101102101131100
A binary sequence generator can be referred to US Patent Publication No. US 2011/0050320 A1 for more detail.
Furthermore, the triplet sequence generator is illustrated by a ring counter to be used by I/O gates, where input values and output values of the triplet sequence generator are shown in Table 2 as follows.
TABLE 2ChipLayerin2in1in0out2out1out00000100110011021101113111011
The specific array generated either by binary sequence generator or by triplet sequence generator is gone through a decoder with a set of corresponding I/O gates to decide which chip layer is corresponding to the CS command.
As shown in FIG. 1, a chip layer 200 in a conventional 3D IC assembly has a conventional decoder 260 and a plurality of I/O gates 231. The array generated by a binary sequence generator is input into the decoder 260 where the input values are sent through input nodes C0 and C1. The output values sent through output nodes (G0, G1, G2, and G3) from the decoder 260 are corresponding to specific arrays to activate the I/O gates 231. For example, when the input values to the decoder 260 of the first chip layer are (0, 0), then the corresponding array of the first chip layer sent from the decoder 260 are (G0, G1, G2, G3)=(1, 0, 0, 0).
Therefore, after decoding by the decoder 260, only the I/O gates 231 of the first chip layer are activated and the rest of the I/O gates of other chip layers are not activated so that only CS1 enters the allocated chip layer to be CS for the first chip layer and accept and react all signals from the controller with the corresponding functions and operation.
Similarly, when the input values are (1, 0) and sent to the decoder 260 of the second chip layer, then the corresponding array of the second chip layer sent from the corresponding decoder 260 are (G0, G1, G2, G3)=(0, 1, 0, 0). After decoding by the decoder 260, only the I/O gate 231 of the second chip layer are activated and the rest of the I/O gates of other chip layers are not activated so that only CS2 enters the second chip layer to be CS for the second chip layer and accept and react all signals from the controller with the corresponding functions and operation. In the same way with the same algorithm, the third chip layer and the fourth chip layer only accept CS3 and CS4 as CS commands to accept and react all signals from the controller with the corresponding functions and operation.
This above mentioned algorithm with the control methodology is quite different from the one using staggered interconnection of CS signals achieved by physical 3D IC package structure. However, no matter I/O gates signals (G0, G1, G2, G3) are selected either by direct assignment or by a sequence generator, the existing control methodology is to assign a group of CS signals to each chip layer activated by the commands sent by the controller to the corresponding chip layer for the corresponding functions and operation where the chip coding sequence has to be strictly corresponding to the stacking sequence of 3D IC. Once there is a failed chip layer or failed chip layers among the 3D IC, the whole 3D IC would be malfunctioned and discarded leading to poor overall yield issues.
FIG. 2 is an illustration of 3D IC fabrication processes of a conventional wafer-level stacked chip assembly where it is clearly illustrated that all the individual chip layers 200 have to be tested first to be KGD and only can be vertically stacked after singulation including vertically stacking a plurality of chip layers 200 on a substrate 40 with a controller 30 adjacent to the stacked chip assembly to drive the desired chip layer 200. Once there are one or several failed chip layers, the whole stacked chip assembly is malfunctioned and discarded.